Analysis of Sub Threshold to above Threshold Leakage Reduction Technique for CMOS At 65nm
نویسندگان
چکیده
منابع مشابه
Analysis of Sub Threshold to above Threshold Leakage Reduction Technique for CMOS At 65nm
In this paper, a dual supply level shifter is designed for robust voltage shifting from sub threshold to above threshold domain using high voltage CMOS technique. High voltage CMOS is an effective circuit level technique that improves the performance and design by utilizing high threshold voltage. In this minimum input voltage attainable while maintaining robust operation is found to be around ...
متن کاملAnalysis of Sub Threshold to above Threshold Leakage Reduction Technique for CMOS At 65nm
In this paper, a dual supply level shifter is designed for robust voltage shifting from sub threshold to above threshold domain using high voltage CMOS technique. High voltage CMOS is an effective circuit level technique that improves the performance and design by utilizing high threshold voltage. In this minimum input voltage attainable while maintaining robust operation is found to be around ...
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Previous efforts to reduce SRAM power have included voltage scaling to the edge of sub-threshold [2] or into the sub-threshold region [3], but only for idle cells. Although some published SRAMs operate at the edge of sub-threshold, none function at sub-threshold supply voltages compatible with logic operating at the minimum energy point. The 0.18μm memory in [4] provides one exception. Consisti...
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A new dual-threshold circuit technique is proposed in this paper for reducing the subthreshold and gate oxide leakage currents in idle and non idle mode of operation for footerless domino circuits. In this technique a p-type and an n-type lea-kage controlled transistors (LCTs) are introduced between the pull-up and pull-down network and the gate of one is controlled by the source of the other. ...
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A novel technique for dualthreshold is proposed and examined with inputs and clock signals combination in 65nm dualthreshold footerless domino circuit for reduced leakage current. In this technique a p-type and an n-type leakage controlled transistor (LCTs) are introduced between the pull-up and pull-down network and the gate of one is controlled by the source of the other. A high-threshold tra...
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ژورنال
عنوان ژورنال: International Journal of Computer Applications
سال: 2014
ISSN: 0975-8887
DOI: 10.5120/18292-9021